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The process of semiconductor manufacturing consists of wafer fabrication (Wafer Fabr ication), wafer probe/Sorting, chip packaging (Assemble), test (Test), and storage of finished products (Finish Goods).
The manufacturing process of conductor devices is divided into front and back processes. Wafer manufacturing and testing are called Front End processes, while chip packaging, testing and finished product storage are called Back End processes. , The former and the latter are generally handled separately in different factories.
The previous process is to start from the whole silicon wafer through repeated filming, oxidation, and diffusion, including photo-engraving and photolithography, to make transistors, integrated circuits and other semiconductor components and electrodes, etc., to develop the electronic functions of the materials , In order to achieve the required component characteristics.
The latter process starts with the chips that are cut from the silicon wafer one by one, and performs the processes of mounting, fixing, bonding, plastic potting, drawing out the terminal, and printing inspection to complete the packaging of devices and components. Body to ensure the reliability of components and facilitate the connection with external circuits.
Wafer manufacturing
Wafer manufacturing is mainly to make circuits and inlaid electronic components (such as transistors, capacitors, logic gates, etc.) on the wafer. It is a process that requires complex technology and high capital investment. Taking a microprocessor as an example, the required processing steps can reach hundreds of times, and the required processing machines are advanced and expensive. Although the detailed processing procedures are constantly changing with changes in product types and use technologies, the basic processing steps are usually that the wafers are properly cleaned, followed by oxidation and deposition, followed by lithography, etching, and ionization. Repeated steps such as implantation, finally complete the processing and production of the circuit on the wafer.
Wafer test
After the wafer undergoes the dicing process, a small grid will be formed on the surface, and each small grid is a chip or die (Die), that is, an independent integrated circuit. In general, the chips produced on a wafer have the same specifications, but it is also possible to produce chips with different specifications and levels on the same wafer. Wafer testing needs to complete two tasks: one is to conduct acceptance testing on each wafer, and use a probe to detect whether each wafer is qualified, and the unqualified wafers will be marked for the purpose of cutting the wafer. The unqualified wafers are screened out; the second is to conduct electrical characteristics (such as power, etc.) inspection and grouping of each wafer, and make corresponding distinguishing marks.
Chip packaging
First, attach the diced wafer to the frame substrate with glue; secondly, use ultra-fine metal wires or conductive resin to connect the bonding pads of the chip to the pins of the frame pad to make the chip and The external circuits are connected to form an integrated circuit chip (Bin) of a specific specification; then the independent chip is packaged and protected with a plastic shell to protect the chip components from external force damage. After molding, a series of operations must be performed, such as Post Mold Cure, Trim, Form, and Plating.
Chip test
The packaged chip needs to undergo in-depth testing after successfully passing through the Burn In. The testing includes Initial Test and Final Test. The initial test is to put the packaged chips in various environments to test their electrical characteristics (such as operating speed, power consumption, frequency, etc.), select the failed chips, and divide the normally working chips into different levels according to their electrical characteristics. Post-testing is to perform operations such as switching between levels of the chip after the initial test.
Product storage
The tested chips go through the semi-finished product warehouse and enter the final processing, including laser printing, factory quality inspection, and finished product packaging, etc., and then enter the warehouse.
Microelectronics Packaging and Packaging Engineering
Packaging (packaging, PKG): mainly completed in the back-end engineering of semiconductor manufacturing. That is, the use of film technology and micro-connection technology to arrange, fix and connect semiconductor components and other components on the frame or substrate, lead out the connection terminals, and potting and fixing with a plastic insulating medium to form the overall main structure.
Packaging engineering: is the sum of packaging and mounting engineering and substrate technology. The science and technology that transform the electronic and physical functions of semiconductors and electronic components into a form suitable for machines or systems and make them serve the human society, collectively referred to as electronic packaging engineering.
The history of the term encapsulation used in electronic engineering is not long. In the era of vacuum tubes, mounting electronic tubes and other devices on the tube sockets to form circuit equipment is generally called assembly or assembly. At that time, there was no concept of packaging. Since the emergence of semiconductor components such as transistors and ICs, the history of electronic engineering has changed. On the one hand, these semiconductor components are small and soft; on the other hand, their performance is high, and they are multi-functional and multi-specification. In order to give full play to its functions, it needs to be reinforced, sealed, and enlarged in order to achieve a reliable electrical connection with an external circuit, and obtain effective mechanical support, insulation, signal transmission and other aspects of protection. The concept of "encapsulation" appeared on this basis.
The basic function of the package is to protect the circuit chip from the surrounding environment (including physical and chemical influences). Therefore, in the initial microelectronics packaging, a metal can (Metal Can) was used as the shell, and the fragile electronic components were protected by a completely isolated and airtight method from the outside world. However, with the development of integrated circuit technology, especially the continuous improvement of chip passivation layer technology, the function of the package is gradually alienating.
Maintaining the electrical characteristics of the chip
Microelectronics packaging engineering and electronic substrates
Level 3 (board or card)
It refers to the assembly process that constitutes a board or card. Multiple single-chip packages and MCMs that complete level 2 are mounted on a multi-layer substrate such as a PCB board, and plug-in terminals are provided around the substrate for electrical connection with the motherboard and other boards or cards.
Level 4 (unit component)
Multiple boards or cards that complete level 3 are mounted on a large PCB called a mother board through plug-in terminals on them to form a unit assembly.
Level 5 (framework)
It is a frame (frame) composed of multiple units, and the units are connected by wiring or cables.
Level 6 (Final assembly, complete machine or system)
It is to arrange multiple racks side by side, and the racks are connected by wiring or cables to form a large electronic device or electronic system.
Package substrate and package classification
Zero-level packaging
The production of bare chip electrodes and the connection of leads are all done on the silicon wafer, which has nothing to do with the substrate for the time being.
First level package
First-level packaging Single-chip or multi-chip packaging via level 0 packaging on packaging substrates (ordinary substrates, multi-layer substrates, HDI substrates) to form integrated circuit modules (or components). That is, how the chips are loaded on various substrates (or interposers).
Second-level packaging
The second-level package integrated circuit (IC component or IC block) is packaged on a package substrate (ordinary substrate, multi-layer substrate, HDI substrate) to form a board or card. That is, various mounting methods (two-level packaging or one-level plus two-level packaging). The DIP and PGA mentioned later belong to the DIP sealing type, and the GFP, BGA, CSP, etc. belong to the SMT mounting type, which belong to the second-level package.
Three-level packaging
The three-level package contains 4, 5, and 6 levels. That is, multiple boards or cards that have completed level 3 are mounted on a large PCB called a mother board (or carrier board) through the plug-in terminals on them to form unit components (this level is also one of the mounting methods); or Multiple units are formed into a rack, and the units are connected with wiring (rigid-flex PCB) or cables; or multiple racks are arranged side by side, and the racks are connected by wiring (rigid-flex PCB) or cables. This constitutes a large-scale electronic equipment or system (the two levels are called assembly).
Wafer dicing
First, the wafer is fixed on the support ring with a film to ensure that the wafer is fixed during cutting, and then the wafer is cut into very tiny particles according to the existing unit format. Deionized water is required for cutting. The temperature produced by cooling and cutting, and itself is anti-static.
Wafer Paste
The purpose of wafer pasting is to paste the cut wafer particles on the wafer temple of the lead frame with silver paste, and mount the cut chips on the middle dry plate of the lead frame with adhesive. Usually epoxy (or polyimide) is used as a filler to increase the thermal conductivity of the adhesive.
Gold wire bonding
The purpose of gold wire bonding is to connect the bonding pressure points on the wafer and thin gold wires to the inner pins on the lead frame, so that the circuit of the wafer is connected to the pins. One end of the commonly used gold wire is fired into a small ball, and then the small ball is bonded to the first solder joint. Then pull the gold wire according to the set procedure, and bond the gold wire to the second solder joint.
Plastic package
Place the wire-bonded chip and the lead frame in the mold cavity, and then inject the molding compound epoxy resin to wrap the gold wire on the wafer and the lead frame. This is to protect wafer components and gold wires. The molding process is divided into two stages: heating injection molding and molding. The main purpose of plastic encapsulation is: to protect the components from damage; to prevent gas from oxidizing the internal chip; to ensure the safety and stability of the product.
laser printing
Laser printing is the use of laser rays to print logos and numbers on the surface of the plastic encapsulant. Including manufacturer's information, device code, packaging date, can be used for identification and traceability.
Cut tendons and bend
Cut and separate the outer pins of the lead frame that were originally connected together, and bend them into the designed shape, but do not break the epoxy sealing state, and avoid the distortion of the pins, and put the cut products into the barrel or tray Convenient for transportation.
test
Inspect whether the appearance of the product can meet the design and standards. Common test items include: whether the printed characters are clear and correct, the flatness of the pins, the coplanar line, the pitch between the pins, whether the plastic package is damaged, electrical performance and other functional tests, etc.
Semiconductor packaging technology and process
The essence of chip packaging:
Chip packaging in the traditional sense generally refers to the packaging shell used to place the integrated circuit chip. It can also include the process of forming packages with different shapes from wafer dicing, different types of chip pin holders and packaging materials. From a physical perspective, its basic function is to provide a stable environment for the integrated circuit chip to protect the chip from external harsh conditions (such as dust, moisture). From an electrical perspective, chip packaging is also a link for information exchange between the chip and external circuits. It needs to establish a low-noise, low-delay signal loop between the chip and the external circuit.
However, no matter how the packaging technology develops, in the final analysis, the chip packaging technology uses a certain connection method to connect the pins on the wafer slice with the lead frame and the pins on the package shell or package substrate to form a chip. The essence of packaging is to avoid the influence of external negative factors on the internal circuit of the chip, and to connect the chip to the external circuit, of course, also to make the chip easy to use and transport.
Chip packaging technology is becoming more and more advanced, the tube angular spacing is getting smaller and smaller, the pin density is getting higher and higher, the resistance of chip packaging to temperature changes is getting better and better, and the reliability is getting higher and higher. Another important indicator is to look at the ratio of chip to package area.
In addition, a major problem in packaging technology is the area occupied by the chip, that is, the area of the printed circuit board (PCB) occupied by the chip. From the early DIP package to the current mainstream CSP package, the area ratio of the chip to the package can reach 1:1.14, which is very close to the ideal value of 1:1. And more advanced MCM to SiP packaging, from planar stacking to vertical stacking, the chip and package area are the same to further improve performance.
Various commonly used packages
Inside the package
The first stage (before the 1970s)
Mainly through-hole plug-in package; typical package forms include the initial metal circular (TO type) package, and later ceramic dual in-line package (CDIP), ceramic-glass dual in-line package (Cer DIP) ) And plastic dual-in-line package (PDIP), etc.; among them, PDIP, due to its excellent performance, low cost, and suitable for mass production, has become the mainstream product at this stage.
The second stage (after the 1980s)
The transition from a through-hole plug-in package to a surface-mount package, from a flat two-sided lead package to a flat four-sided lead package. Surface mount technology is known as a revolution in the field of electronic packaging and has been developed rapidly. Correspondingly, some packaging forms adapted to surface mount technology, such as plastic leaded chip package (PLCC), plastic quad flat package (PQFP), plastic small outline package (PSOP) and leadless quad flat package ( PQFN) and other packaging forms came into being and developed rapidly. Among them, PQFP, due to its high density, small lead pitch, low cost and suitable for surface mounting, became the leading product in this period.
The third stage (after the 1990s)
The development of semiconductors has entered the era of ultra-large-scale semiconductors, with feature sizes reaching 0.18-0.25 µm, requiring semiconductor packaging to develop in the direction of higher density and higher speed. Therefore, the lead method of semiconductor packaging has developed from a flat four-sided lead type to a flat ball grid array type package, and the lead technology has developed from a metal lead to a miniature solder ball.
In this context, the solder ball array package (BGA) has developed rapidly and has become a mainstream product. According to the different packaging substrates, BGA can be divided into plastic ball array package (PBGA), ceramic ball array package (CBGA), carrier tape ball array package (TBGA), heat sink ball array package (EBGA), and flip chip Chip solder ball array package (FC-BGA), etc.
In order to meet the needs of small, light, thin and low-cost portable electronic products such as mobile phones and notebook computers, chip-scale packaging (CSP) has been developed on the basis of BGA; CSP also includes lead frame CSP, flexible interposer CSP, rigid Various forms such as plug-in board CSP and wafer-level CSP are currently in a stage of rapid development.
At the same time, multi-chip components (MCM) and system packaging (SiP) are also booming, which may give birth to the next revolutionary change in electronic packaging. According to different substrate materials, MCM is divided into multilayer ceramic substrate MCM (MCM-C), multilayer film substrate MCM (MCM-D), multilayer printed circuit board MCM (MCM-L) and thick film mixed substrate MCM (MCM- C/D) and other forms. SiP is developed to meet the needs of miniaturization of the whole system and improve the function and density of semiconductors. SiP uses mature assembly and interconnection technology to integrate various integrated circuits such as CMOS circuits, GaAs circuits, SiGe circuits or optoelectronic devices, MEMS devices, and various passive components such as resistors, capacitors, and inductors into a package to achieve The function of the whole machine system.
At present, semiconductor packaging is in the third stage of maturity and rapid growth, and the major packaging forms such as BGA/CSP have begun to enter the stage of large-scale production. At the same time, the fourth technological change with SiP and MCM as the main development direction is in the embryonic stage.
The sealing or packaging methods of semiconductor components are divided into two categories: airtight packaging and resin packaging, and airtight packaging can be divided into metal packaging, ceramic packaging and glass packaging. The purpose of sealing and packaging is to isolate from the external temperature, humidity, atmosphere and other environments. In addition to protection and electrical insulation, it also plays a role in outward heat dissipation and stress relaxation. Generally speaking, hermetic packaging has high reliability but high price. At present, due to the improvement of packaging technology and materials, resin packaging has an absolute advantage, but in some special fields (military industry, aviation, aerospace, navigation, etc.), airtight packaging is essential.
According to packaging materials, it can be divided into: metal packaging, ceramic packaging (C), and plastic packaging (P). Semiconductor products using the first two packages are mainly used in the aerospace, aviation and military fields, while plastic packaged semiconductor products have been widely used in the civilian field. At present, resin packaging has accounted for 98% of the world's integrated circuit packaging market, and more than 97% of semiconductor devices are packaged in resin packaging. In the field of consumer circuits and devices, resin packaging basically dominates the world, and more than 90% of the plastic packaging materials are Epoxy resin molding compound and epoxy liquid potting compound.
There are three common chip electrical interconnection methods, namely wire bonding, carrier tape automatic welding and flip-chip welding.
Generally, although the electrical performance of TAB and FC interconnection is better, they both require additional equipment. Therefore, for chips with a small number of I/Os, the cost of TAB and FC is very high. In addition, in 3D packaging, due to chip stacking, the stacked chips cannot all be flipped on the package body, and can only pass between the WB and the package body. Interconnect between. For these reasons, WB has been the mainstream technology of chip interconnection so far, and it occupies a very important position in chip electrical interconnection.
Wire Bonding (WB)
Wire bonding (WB) is to connect the chip pads and the corresponding pads on the package body with thin metal wires one by one, one at a time. It is a simple chip electrical interconnection technology, according to the electrical connection method. Seems to belong to wired bonding.
Carrier tape automatic welding (TAB)
Tape Automated Bonding (TAB) is an IC assembly technology that mounts and interconnects ICs to flexible metalized polymer carrier tapes. The inner lead of the carrier tape is bonded to the IC, and the outer lead is bonded to the conventional package or PCB. The entire process is automatically completed, so the efficiency ratio is higher. According to the electrical connection method, it belongs to the wireless bonding method.
Flip Chip Bonding (FC)
Flip chip bonding (FC) refers to the connection of the active side of the integrated circuit chip with the carrier or substrate. The interconnection between the chip and the substrate is realized by the bump structure on the chip and the bonding material on the substrate. In this way, both mechanical interconnection and electrical interconnection can be realized at the same time. At the same time, in order to improve the reliability of the interconnection, an underfill is added between the chip and the substrate. For high-density chips, flip-chip bonding has strong advantages in terms of cost and performance. It is the development trend of chip electrical interconnection. According to the electrical connection method, it belongs to the wireless bonding method.
According to the arrangement of the package pins, the connection method of the chip and the PCB board, and the time sequence of development, semiconductor packages can be divided into two categories: PTH package (Pin-Through-Hole) and SMT package (Surface-Mount-Technology). It is usually called the jack type (or through-hole type) and surface mount type.
Pin Insertion Technology (PTH):
Pin-insertion packaging, as the name implies, uses the insertion method during the connection between the chip and the target board. The ancient and classic DIP package belongs to this type of packaging. In the early integrated circuits, due to the low degree of chip integration and fewer input/output pins required for chip operation, this type of packaging is often used. There are two derivative packaging forms of DIP package, namely: SiP and ZIP, which are just to adapt to different application fields. The traditional DIP package is slightly improved in the pin arrangement and shape of the package shell.
Surface Mount Package (SMT):
The advantages of PTH packaging in terms of mechanical connection strength are beyond doubt, but at the same time it also brings some negative effects. The through holes used in the PTH package will occupy a large amount of the effective wiring area of the PCB board, so the current mainstream PCB board design mostly uses the surface mount package.
There are many types of surface mount packages. Commonly used packages are:
Small Outline Transistor (SOT)
Small pinout package (Smal lOutline Package, SOP)
Quad Flat No-lead Package (QFN)
Thin Small Shrink Outline Package (TSSOP)
Quad Flat Package (QFP)
Quad Flat No-lead Package (QFN)
From SOT to QFN, the number of pins supported by the chip package is increasing, and the corner pitch of the chip package is getting smaller and smaller.
The advantage of the surface mount package is that the size of the chip package is greatly reduced, and the pin density of the chip package is greatly improved. When the number of pins is the same as that of the PTH package, the package size of the surface mount package will be much smaller than that of the PTH package. The surface mount package only occupies the wiring space on the surface of the PCB board. When the multilayer wiring process is used, the effective wiring area occupied by the package is greatly reduced, which can greatly improve the wiring density and utilization of the PCB board.
BGA:
With the continuous improvement of chip integration, the number of input/output pins required by the chip has been further increased in order to enable the chip to achieve more complex functions. Faced with the increasing number of pins and the decreasing chip package size, microelectronics Packaging proposes a new packaging form BGA package.
The bottom of the BGA package is made of pins in a matrix manner. The shape of the pins is spherical. The chip is assembled on the front of the package. Sometimes the BGA chip and the spherical pins are placed on the same side of the substrate. BGA packaging is a commonly used packaging form for large-scale integrated circuits. BGA packages can be divided into three categories according to the material of the package substrate: plastic BGA, ceramic BGA, and carrier tape BGA.
The BGA package has the following common features:
The failure rate of chip packaging is low;
Improve the ratio of the number of device pins to the size of the package, and reduce the area of the substrate;
Pin coplanarity is better, reducing soldering defects caused by pin coplanar damage;
BGA pins are solder value balls, and there is no pin deformation problem;
BGA package pins are shorter, the input/output signal link is greatly shortened, the resistance/capacitance/inductance effects introduced by the pin length are reduced, and the parasitic parameters of the package shell are improved;
The BGA ball grid array has more contact points with the PCB board, and the contact area is larger, which is conducive to the heat dissipation of the chip, and the BGA package is conducive to improving the packaging density of the package.
The BGA package uses a matrix pin arrangement. Compared with the traditional SMD package, the package size of the BGA package can be made smaller with the same number of pins, and at the same time it saves the wiring area of the PCB board.
CSP definition
According to the definition of the J-STD-012 standard, CSP refers to an advanced package with a package size that does not exceed 1.2 times the bare chip. It is generally believed that CSP technology is a packaging technology produced by further miniaturization of various package sizes in the process of further upgrading the existing chip packaging technology, especially the mature BGA packaging technology.
CSP technology can ensure that under the premise of high performance and high reliability, the VLSI can achieve a package size close to that of a bare chip at a low cost. Compared with the QFP package, the CSP package size is less than 1/10 of the QFP package with a pin pitch of 0.5mm; compared with the BGA package, the CSP package size is about 1/3 of the BGA package.
When the package size is fixed, if you want to further increase the number of pins, you need to reduce the pin spacing. Restricted by the existing technology, there are process limits for different packaging forms. For example, the BGA package matrix-type value ball can be as high as 1000, but the CSP package can support more than 2000 pins.
The main structure of CSP includes core chip, interconnection layer, solder balls (or bumps, solder pillars), protective layer, etc. The chip and package shell are connected to the interconnection layer mechanically and electrically. Among them, the interconnection layer realizes the internal connection between the chip and the solder ball through methods such as carrier tape automatic welding, wire bonding, and flip chip, and is a key component of CSP.
At present, there are a variety of packaging structure forms that conform to the CSP definition, and their characteristics are:
The ratio of the chip area to the package area of CSP is very close to the ideal situation of 1:1. The absolute size is 32mm2, which is equivalent to one-third of BGA and one-sixth of TSOP. That is, CSP can increase the memory capacity by 3 to 6 Times more.
The test results show that CSP can conduct 88.4% of the chip's working heat to the PCB with a thermal resistance of 35°C/W-1, while TSOP can only conduct 71.3% of the total heat with a thermal resistance of 40°C/W-1.
The center ball pin form used by CSP can effectively shorten the signal conduction distance, and the signal attenuation is also reduced. The chip has stronger anti-interference and anti-noise performance, and the access time is reduced by 15% to 20% compared with BGA. Meet the actual needs of ultra-high frequency memory chips such as DDRⅡ, DRDRAM, etc.
CSP can easily produce more than 1000 signal pins. Even complex memory chips can be packaged. With the same number of pins, the assembly of CSP is much easier than that of BGA. CSP can also perform comprehensive burn-in, screening, and testing, and is easy to operate and trim, and can obtain real KGD (Known GoodDie known qualified chips) chips.
